Status registers are often used to store status information relating to the internal operations of a semiconductor integrated circuit (“IC”). Memory ICs or devices, such as flash electrically erasable programmable read only memory (“EEPROM”) devices, may store information in a status register to indicate whether an operation (e.g., an erase operation, a programming operation, a read operation, etc.) is in progress or is completed. The status register may also indicate whether a specific operation has been completed successfully or unsuccessfully. Such information often provides necessary or desirable information to other components in a system.
For example, the processor or CPU in a system may need to know when an erase operation performed on a memory device (such as a flash memory device) is completed before requesting the memory device to perform a programming operation. Additionally, the processor in a system may want to know whether an erase operation to a specific memory location has been suspended. Typically, an erase operation takes a much longer time to complete as compared to a programming or read operation. For example, an erase operation may take a few milliseconds (“ms”), whereas a programming operation may take 7–8 microseconds (“μs”) and a reading operation may take 85 nanoseconds (“ns”). Thus, when an erase operation to a specific memory location is suspended, the processor may program or read data from a different memory location rather than waiting for the completion of the current erase operation. The ability to suspend an erase operation may improve the overall performance of a flash memory device.
Typically, a status register stores multiple memory bits in which one or more of the memory bits may be used to provide a specific status signal. The status signal may be sent as an output from the memory device via a designated output pin when polled or via the data input/output (“I/O”) pins of a memory device in response to a read status register command.
FIG. 1 illustrates one embodiment of a status register for a prior art flash memory device that is capable of performing programming, erase, and read operations. The status register 100 includes the five memory locations 101 through 105 with each memory location storing at least one memory bit. For the embodiment shown in FIG. 1, the status register 100 provides five status signals. The memory location 101 stores Vpp status (“VPPS”) information; the memory location 102 stores byte write and set lock bit status (“BWSLBS”) information; the memory location 103 stores erase and clear lock bits status (“ECLBS”) information; the memory location 104 stores erase suspend status (“ESS”) information; and the memory location 105 stores write state machine status (“WSMS”) information.
The VPPS information indicates whether Vpp, the programming voltage, is at an acceptable voltage level or not at an acceptable voltage level. If Vpp is not at an acceptable voltage level, then the current operation may be aborted. The BWSLBS information indicates an unsuccessful byte write operation or a successful byte write operation. Alternatively, the BWSLBS information indicates an unsuccessful set master/block lock bit operation or a successful set master/block lock bit operation. The ECLBS information indicates an unsuccessful block erasure operation or a successful block erasure operation. Alternatively, the ECLBS information indicates an unsuccessful clear lock bits operation or a successful clear lock bits operation. The ESS information indicates that the block erase operation is suspended or that the block erase operation is in progress/completed. The WSMS information indicates that the write state machine is ready or is busy.
The VPPS signal, the BWSLBS signal, the ECLBS signal, the ESS signal, and the WSMS signal are provided are outputted in response to a read status register command. Furthermore, the WSMS signal is outputted by polling a dedicated status output pin (e.g., pin).
The prior art memory device described above did not, however, provide the feature of suspending a programming operation. Therefore, a programming operation specifying a particular memory location could not be suspended in order to perform another operation, such as a read operation to another memory location, while the programming operation is suspended. In certain situations, it may be more efficient to perform a read operation (which requires less time than a write operation) while a programming operation is suspended, rather than waiting until the programming operation is completed.
Additionally, the prior art memory device described above did not provide the feature of indicating whether an unsuccessful program or erase operation was due to an attempt to access data in a protected memory block. A prior art protection mechanism was implemented by the setting and clearing of memory bits (i.e., lock bits) that correspond to the various memory blocks in the memory device. The lock bits are stored in a miniature array referred to as the block lock mini-array. The lock bits within the block lock mini-array are set to indicate that the corresponding memory block is locked, and cleared (or not set) to indicate that the corresponding memory block is unlocked. A read, program, or erase operation may be performed on any unlocked memory block. A program or erase operation may not, however, be performed on any locked memory block unless an override lock operation is first performed on the locked memory block